The present invention relates generally to the manufacture and testing of integrated circuit devices and, more particularly, to a method and apparatus for determining the electromigration characteristics of integrated circuit interconnect material.
Integrated circuits are typically fabricated with multiple levels of patterned metallization lines, electrically separated from one another by interlayer dielectrics containing vias at selected locations to provide electrical connections between levels of the patterned metallization lines. As these integrated circuits are scaled to smaller dimensions in a continual effort to provide increased density and performance (e.g., by increasing device speed and providing greater circuit functionality within a given area chip), the interconnect linewidth dimension becomes increasingly narrow, which in turn renders them more susceptible to deleterious effects such as electromigration.
Electromigration is a term referring to the phenomenon of mass transport of metallic atoms (e.g., aluminum) which make up the interconnect material, as a result of electrical current conduction therethrough. More specifically, the electron current collides with the metal ions, thereby pushing them in the direction of current travel. Over an extended period of time, the vacated atoms tend to cause void formations typically at one end of a line, whereas the accumulation of atoms at the other end of the line tend to cause hillock formations. Such deformation increases line resistance and, in some instances, leads to open circuits, short circuits and device failure. This phenomenon becomes increasingly more significant in integrated circuit design, as relative current densities through metallization lines continue to increase as the linewidth dimensions shrink.
Package-level testing is generally used in industry to evaluate the electromigration (EM) reliability of metal interconnects. For this purpose, standard test structures and test methodologies have been defined and implemented. These package-level tests are typically performed under moderately accelerated stress with expensive, specialized equipment and at elevated temperatures produced in an oven. Based on collected time to failure data, the lifetimes under field conditions are then estimated by using Black""s equation for determining the acceleration factor in the EM tests.
However, as integrated circuit technology evolves, the interconnect systems therein become more complicated, which results in an increasing number of process modules to be evaluated for reliability assurance. Competitive pressures have correspondingly increased the need to shorten EM testing times (which are typically on the order of 10 to 100 hours for package-level testing). Accordingly, in order to reduce test time, wafer-level testing has been implemented as an alternative to package level testing.
Wafer-level testing is usually conducted using a probe station, and produces reduced fail times on the order of seconds to minutes. In so doing, the wafer tests involve introducing high current densities on the order of about 1xc3x97107 A/cm2. Another significant difference between wafer-level testing and package-level testing is the fact that, in wafer-level testing, the elevated temperature conditions are created by Joule heating (from the applied stress current) and not through external oven heating.
One example of a wafer-level test technique is what is known as the xe2x80x9cSWEATxe2x80x9d (Standard Wafer-level Electromigration Acceleration Test), in which a relatively large current is passed through a metal test structure. With this particular test, it is desired to maintain a constant xe2x80x9ctime to failurexe2x80x9d from test to test. Other types of wafer-level tests include an isothermal (constant temperature) test and a constant current test. Unfortunately, the rapidity with which these wafer-level tests are performed, combined with the uncertainty of temperature associated with Joule heating, effectively limits the test""s usefulness to being a xe2x80x9cspot checkxe2x80x9d for monitoring the quality of wafer lots in real time. In other words, because of the difficulty with independently controlling temperature and current in wafer-level testing, lifetime projections produced by these methods are untrustworthy.
Another drawback associated with some conventional wafer-level testing is that the test structures themselves are typically fabricated with a single level of metal. However, such single-level metal structures are not representative of actual structures found on a product chip. In particular, they do not incorporate interlevel connections such as studs or vias, and thus are not suited for determining lifetime projections of structures on chips. Moreover, structures incorporating studs and vias can suffer from additional temperature non-uniformity due to selective heating of the line caused by geometric effects or materials differences.
The foregoing discussed drawbacks and deficiencies of the prior art are overcome or alleviated by a method for determining the electromigration characteristics of a wiring structure in an integrated circuit device. In an exemplary embodiment of the invention, the method includes configuring a defined test structure type for the integrated circuit device. The defined test structure type further includes a first line of wiring primarily disposed in a principal plane of a semiconductor substrate, and a second line of wiring connected to the first line of wiring. The second line of wiring is disposed in a secondary plane which is substantially parallel to the principal plane, with the first and second lines of wiring being connected by a via structure therebetween. A thermal coefficient of resistance for the first line of wiring and the via structure is determined, and a wafer-level stress condition is introduced in a first individual test structure of the defined test structure type. Then, at least one parameter value is determined for the first individual test structure, which parameter value is used to predict a lifetime projection for the wiring structure in the integrated circuit device.
In a preferred embodiment, a package-level stress condition is introduced in a second individual test structure of the defined test structure type. At least one parameter value for the second individual test structure is determined, and the at least one parameter value determined for the second individual test structure is correlated with the at least one parameter value determined for the first individual test structure.
In another embodiment, the defined test structure type includes a first line of wiring disposed in a principal plane of a semiconductor substrate. A second line of wiring is connected to the first line of wiring, the second line of wiring disposed in a secondary plane which is substantially parallel to the principal plane. In addition, a heat sink structure is located adjacent to the first line of wiring, the heat sink structure being capable of dissipating heat associated with passage of electrical current through the first line of wiring. Preferably, the first line of wiring includes a first end connected to a second end through an elongated section therebetween. The second line of wiring is connected to the first line of wiring at the first and second ends through metallic studs or vias.